Boundary scan testing is well known in the art. Boundary scan testing uses a plurality of shift registers that are built into each integrated circuit. A boundary scan controller circuit is incorporated into each integrated circuit to control the transfer of data serially from one register to another. One important advantage of boundary scan testing is that it allows testing of internal logic circuitry to be conducted from external terminals, obviating the need for probes and other instrumentation. By way of example, one primary use of boundary scan cell designs is for circuit continuity testing. This type of test involves loading a value into a register and then applying a certain voltage condition to the associated pad to determine if an open or short circuit exists.
An industry standard has been implemented for boundary scan test circuits so that integrated circuits from different manufacturers may be connected in a serial chain within an electronic system. This standard is described in an industry specification, known as the IEEE JTAG 1149.1 standard (IEEE Press, 1991) ("the Standard"). The Standard provides a protocol by which various test functions may be accomplished through specified test ports defined in the specification. For example, in a JTAG scan, test circuitry and five additional JPEG test pins are added to each chip. Essentially, the Standard outlines the details of the serial path of linked test registers (called the boundary scan register chain) through each integrated circuit. Boundary scan cell designs and architectures are described in U.S. Pat. Nos. 5,768,289; 5,491,666; 5,333,139; 5,377,199; 5,448,525; and 5,434,804, each of which are assigned to the assignee of the present application.
The Standard also defines the properties of the boundary scan controller circuit for each integrated circuit. The boundary scan controller circuit controls the transfer of data through the various stages of the shift registers formed by the boundary scan cells within the integrated circuit. During operation, a series of commands are issued through the test pins to read back data and verify that the interconnections have been properly established.
Although boundary scan circuitry has been used extensively in past microprocessor and other integrated circuit designs, the circuitry required to implement a JTAG boundary scan cell in accordance with the full IEEE specification is relatively large and complicated. There still exists a need for a minimal implementation of a JTAG boundary scan cell that provides enhanced testability features.